Phi Beta Lambda Business Club Concord, CA Sep 2009 to Dec 2009 MemberJohn Muir Health Walnut Creek, CA Jun 2008 to Aug 2008 Summer Youth Program InternLongs (CVS) Walnut Creek, CA Apr 2008 to Jun 2008 CashierPanda Express Walnut Creek, CA Dec 2007 to Apr 2008 CashierAnimal Rescue Foundation Walnut Creek, CA Sep 2005 to Feb 2006 Volunteer
Education:
University of California Davis, CA Aug 2012 Bachelor of Arts in Economics
Us Patents
Digital Signal Processing Circuit Having A Pattern Detector Circuit
Vasisht Vadi - San Jose CA, US Jennifer Wong - Fremont CA, US Bernard New - Carmel Valley CA, US Alvin Ching - Sunnyvale CA, US John Thendean - Berkeley CA, US Anna Wong - Santa Clara CA, US James Simkins - Park City UT, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 15/00
US Classification:
708200000
Abstract:
An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.
Digital Signal Processing Block Having A Wide Multiplexer
Bernard New - Carmel Valley CA, US Vasisht Vadi - San Jose CA, US Jennifer Wong - Fremont CA, US Alvin Ching - Sunnyvale CA, US John Thendean - Berkeley CA, US Anna Wong - Santa Clara CA, US James Simkins - Park City UT, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 15/00
US Classification:
708200000
Abstract:
A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.
Architectural Floorplan For A Digital Signal Processing Circuit
Alvin Ching - Sunnyvale CA, US Jennifer Wong - Fremont CA, US Bernard New - Carmel Valley CA, US James Simkins - Park City UT, US John Thendean - Berkeley CA, US Anna Wong - Santa Clara CA, US Vasisht Vadi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708490000
Abstract:
A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.
Digital Signal Processing Circuit Having A Pattern Detector Circuit For Convergent Rounding
Bernard New - Carmel Valley CA, US Jennifer Wong - Fremont CA, US James Simkins - Park City UT, US Alvin Ching - Sunnyvale CA, US John Thendean - Berkeley CA, US Anna Wong - Santa Clara CA, US Vasisht Vadi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708551000
Abstract:
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.
Digital Signal Processing Circuit Having Input Register Blocks
James Simkins - Park City UT, US Jennifer Wong - Fremont CA, US Bernard New - Carmel Valley CA, US Alvin Ching - Sunnyvale CA, US John Thendean - Berkeley CA, US Anna Wong - Santa Clara CA, US Vasisht Vadi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/52
US Classification:
708625000
Abstract:
An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.
Digital Signal Processing Circuit Having A Pre-Adder Circuit
James Simkins - Park City UT, US John Thendean - Berkeley CA, US Vasisht Vadi - San Jose CA, US Bernard New - Carmel Valley CA, US Jennifer Wong - Fremont CA, US Anna Wong - Santa Clara CA, US Alvin Ching - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/50
US Classification:
708700000
Abstract:
A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.
Digital Signal Processing Circuit Having An Adder Circuit With Carry-Outs
John Thendean - , US Jennifer Wong - Fremont CA, US Bernard New - Carmel Valley CA, US Alvin Ching - Sunnyvale CA, US James Simkins - Park City UT, US Anna Wong - Santa Clara CA, US Vasisht Vadi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/50
US Classification:
708700000
Abstract:
An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.
Digital Signal Processing Circuit Having A Simd Circuit
James Simkins - Park City UT, US Jennifer Wong - Fremont CA, US Bernard New - Carmel Valley CA, US Alvin Ching - Sunnyvale CA, US John Thendean - Berkeley CA, US Anna Wong - Santa Clara CA, US Vasisht Vadi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708524000
Abstract:
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
Swedish Medical GroupSwedish Neuroscience Institute Specialists Epilepsy Center 550 17 Ave STE 540, Seattle, WA 98122 206-3203492 (phone), 206-3203088 (fax)
Swedish Hospital Neurology Science Institute 550 17 Ave STE 400, Seattle, WA 98122 206-3203494 (phone), 206-3862845 (fax)
Education:
Medical School Mem Univ of Newfoundland, Fac of Med, St Johns, Nfld, Canada Graduated: 1994
Languages:
English
Description:
Dr. Wong graduated from the Mem Univ of Newfoundland, Fac of Med, St Johns, Nfld, Canada in 1994. She works in Seattle, WA and 1 other location and specializes in Neurology. Dr. Wong is affiliated with Swedish Medical Center - First Hill.
in rates is also occurring at a time when the economy is already facing a number of headwinds from a resumption of student loan payments to a strike by autoworkers. Indeed, Bloomberg Economics chief US economist Anna Wong says the US economy is probably on the verge of tipping into a recession.
Date: Oct 05, 2023
Category: Business
Source: Google
POLITICO Playbook: SCOTUS ruling puts Roe v. Wade on the ropes - POLITICO
MEDIA MOVES Bloomberg is adding Stacy-Marie Ishmael as managing editor for crypto, Anna Wong as chief U.S. economist and Adrian Wooldridge as global business columnist. Ishmael most recently was editorial director of the Texas Tribune. Wong most recently was a principal economist at the Federal Re