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Daniel Rodko

age ~44

from Poughkeepsie, NY

Also known as:
  • Dan Rodko
  • Daniel Radko
Phone and address:
15 Misty Ridge Cir, Poughkeepsie, NY 12603
845-2979403

Daniel Rodko Phones & Addresses

  • 15 Misty Ridge Cir, Poughkeepsie, NY 12603 • 845-2979403
  • 9 Pleasant Ln, Wappingers Falls, NY 12590 • 845-2979403
  • New Hamburg, NY
  • Flushing, NY
  • Wappingers Fl, NY

Work

  • Company:
    Ibm
    Aug 2000
  • Position:
    Advisory engineer

Education

  • Degree:
    MEng
  • School / High School:
    Rensselaer Polytechnic Institute
    2001 to 2005
  • Specialities:
    Microelectronics

Skills

Vlsi • Sram • Microprocessors • Logic Design • Aix • Storage Management • Storage Architecture • Timing Closure • Physical Design • Enterprise Storage • Circuit Design • Computer Architecture • Hardware Architecture • Static Timing Analysis • Vhdl • Testing • Very Large Scale Integration

Industries

Computer Hardware

Resumes

  • Daniel Rodko Photo 1

    Advisory Engineer

    view source
  • Location:
    Middle Village, NY
  • Industry:
    Computer Hardware
  • Work:
    IBM since Aug 2000
    Advisory Engineer
  • Education:
    Rensselaer Polytechnic Institute 2001 - 2005
    MEng, Microelectronics
    The Cooper Union for the Advancement of Science and Art 1996 - 2000
    Bachelor of Engineering (B.Eng.), Electrical and Electronics Engineering
  • Skills:
    Vlsi
    Sram
    Microprocessors
    Logic Design
    Aix
    Storage Management
    Storage Architecture
    Timing Closure
    Physical Design
    Enterprise Storage
    Circuit Design
    Computer Architecture
    Hardware Architecture
    Static Timing Analysis
    Vhdl
    Testing
    Very Large Scale Integration

Us Patents

  • Clock Duty Cycle Based Access Timer Combined With Standard Stage Clocked Output Register

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  • US Patent:
    7275194, Sep 25, 2007
  • Filed:
    Feb 11, 2005
  • Appl. No.:
    11/057318
  • Inventors:
    William V. Huott - Holmes NY, US
    Pradip Patel - Poughkeepsie NY, US
    Daniel Rodko - Wappingers Falls NY, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G01R 31/28
  • US Classification:
    714731, 714724, 714744
  • Abstract:
    An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.
  • Merged Misr And Output Register Without Performance Impact For Circuits Under Test

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  • US Patent:
    7305602, Dec 4, 2007
  • Filed:
    Feb 11, 2005
  • Appl. No.:
    11/056575
  • Inventors:
    Yuen H. Chan - Poughkeepsie NY, US
    William V. Huott - Holmes NY, US
    Pradip Patel - Poughkeepsie NY, US
    Daniel Rodko - Wappingers Falls NY, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G01R 31/28
  • US Classification:
    714726
  • Abstract:
    The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L/L master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.
  • Merged Misr And Output Register Without Performance Impact For Circuits Under Test

    view source
  • US Patent:
    7478297, Jan 13, 2009
  • Filed:
    Oct 22, 2007
  • Appl. No.:
    11/876036
  • Inventors:
    Yuen H. Chan - Poughkeepsie NY, US
    William V. Huott - Holmes NY, US
    Pradip Patel - Poughkeepsie NY, US
    Daniel Rodko - Wappingers Falls NY, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G01R 31/28
  • US Classification:
    714726
  • Abstract:
    The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.
  • Bist Address Generation Architecture For Multi-Port Memories

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  • US Patent:
    7536613, May 19, 2009
  • Filed:
    May 11, 2004
  • Appl. No.:
    10/843608
  • Inventors:
    William Vincent Huott - Holmes NY, US
    Pradip Patel - Poughkeepsie NY, US
    Daniel Rodko - Wappingers Falls NY, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G11C 29/00
    G11C 7/10
  • US Classification:
    714718, 36518904, 365201
  • Abstract:
    Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for greater test coverage than the previous method, which simply inverted one of the write address bits to form the read address.
  • Memory Testing System

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  • US Patent:
    8327207, Dec 4, 2012
  • Filed:
    Jun 9, 2010
  • Appl. No.:
    12/797181
  • Inventors:
    Kevin J. Duffy - Highland NY, US
    William V. Huott - Holmes NY, US
    Pradip Patel - Poughkeepsie NY, US
    Daniel Rodko - Poughkeepsie NY, US
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G01R 31/28
  • US Classification:
    714733, 714718, 714726
  • Abstract:
    An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.
  • Array Self Repair Using Built-In Self Test Techniques

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  • US Patent:
    20060174175, Aug 3, 2006
  • Filed:
    Jan 31, 2005
  • Appl. No.:
    11/047419
  • Inventors:
    William Huott - Holmes NY, US
    Franco Motika - Hopewell Junction NY, US
    Pradip Patel - Poughkeepsie NY, US
    Daniel Rodko - Wappingers Falls NY, US
  • International Classification:
    G01R 31/28
  • US Classification:
    714726000
  • Abstract:
    A soft-fuse test algorithm is distributed on-chip from an ABIST engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Each arrays outputs are monitored by a different multiple input signature register (MISR) with an initial data pattern seed that provides a final desired state of the MISR with either all “0”s or all “1”s, allowing for a simple “single-bit” MISR error evaluation of the monitored array. Using the above single-bit MISR error evaluation technique an ABIST test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.
  • Testing Memory Arrays And Logic With Abist Circuitry

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  • US Patent:
    20110296259, Dec 1, 2011
  • Filed:
    May 26, 2010
  • Appl. No.:
    12/787919
  • Inventors:
    Bargav Balakrishnan - Poughkeepsie NY, US
    Pradip Patel - Poughkeepsie NY, US
    Antonio R. Pelella - Highland Falls NY, US
    Daniel Rodko - Poughkeepsie NY, US
  • Assignee:
    INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
  • International Classification:
    G11C 29/12
    G06F 11/27
  • US Classification:
    714718, 714E11169
  • Abstract:
    A method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the integrated circuit device using the ABIST circuitry, wherein both the memory array portion and the logic portion of the integrated circuit are tested at speed.

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