Douglas L Keil

US Patent:

6540885, Apr 1, 2003

Filed:

Mar 28, 2001

Appl. No.:

09/821427

Inventors:

Douglas Keil - Fremont CA
Eric Wagganer - Milpitas CA
Bryan A. Helmer - Fremont CA

Assignee:

Lam Research Corp. - Fremont CA

International Classification:

C23C 1400

US Classification:

20419233, 20419235, 216 38, 216 39, 216 59, 216 67

Abstract:

Methods for etching a trench into a dielectric layer are provided. One exemplary method controls an ion-to-neutral flux ratio during etching so as to achieve a neutral limited regime in an ion assisted etch mechanism where the neutral limited regime causes bottom rounding. The method includes modulating physical sputtering causing microtrenching to offset the bottom rounding so as to produce a substantially flat bottom trench profile. Some notable advantages of the discussed methods of etching a trench into a dielectric layer includes the ability to eliminate the intermediate etch stop layer. Elimination of the etch stop layer will decrease fabrication cost and process time. Additionally, the elimination of the intermediate stop layer will improve device performance.

US Patent:

6630407, Oct 7, 2003

Filed:

Mar 30, 2001

Appl. No.:

09/820689

Inventors:

Douglas Keil - Fremont CA
Jim Bowers - Brookfield CT
Eric Wagganer - Milpitas CA
Rao Annapragada - Union City CA
Tri Le - Milpitas CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21302

US Classification:

438717, 216 47

Abstract:

A semiconductor manufacturing process wherein an organic anti-reflective coating (ARC) is plasma etched with selectivity to an underlying dielectric layer and/or overlying photoresist. The etchant gas is fluorine-free and includes a carbon-containing gas such as CO gas, a nitrogen-containing gas such as N , an optional oxygen-containing gas such as O , and an optional inert carrier gas such as Ar. The etch rate of the ARC can be at least 10 times higher than that of the underlying layer. Using a combination of CO and O with N and a carrier gas such as Ar, it is possible to obtain dielectric:ARC selectivity of at least 10. The process is useful for etching contact or via openings in damascene and self-aligned contact or trench structures.

US Patent:

6780569, Aug 24, 2004

Filed:

Feb 4, 2002

Appl. No.:

10/068282

Inventors:

Eric Hudson - Berkeley CA
Reza Sadjadi - Saratoga CA
Daxing Ren - Fremont CA
Wan-Lin Chen - Sunnyvale CA
Douglas Keil - Fremont CA
Peter Cirigliano - Sunnyvale CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

G03F 700

US Classification:

430313, 430311, 430330

Abstract:

A method for creating semiconductor devices is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. Polymers in the patterned photoresist layer are chemically cross-linked by exposure to at least one reactive chemical. The pattern in the photoresist layer is transferred to the wafer. A reaction chamber for processing a wafer with a patterned layer of photoresist material, wherein the photoresist material was patterned by exposing the photoresist material using light of a wavelength less than 248 nm is provided. A chamber is provided with a central cavity. A wafer support for supporting the wafer in the central cavity is provided. A cross-linking reactive chemical source in fluid contact with the chamber and which provides a reactive chemical which causes cross-linking of the photoresist is provided.

US Patent:

7022611, Apr 4, 2006

Filed:

Apr 28, 2003

Appl. No.:

10/426043

Inventors:

Douglas L. Keil - Fremont CA, US
Wan-Lin Chen - Sunnyvale CA, US
Eric A. Hudson - Berkeley CA, US
S. M. Reza Sadjadi - Saratoga CA, US
Mark H. Wilcoxson - Piedmont CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/302

US Classification:

438706, 438705, 438709, 438710, 438725, 430296, 430313, 430328

Abstract:

A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

US Patent:

7319316, Jan 15, 2008

Filed:

Jun 29, 2005

Appl. No.:

11/172014

Inventors:

Christopher Kimball - Fremont CA, US
Eric Hudson - Berkeley CA, US
Douglas Keil - Fremont CA, US
Alexei Marakhtanov - Albany CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

C02F 1/00

US Classification:

324 7676, 324 7611, 324 7665, 324 7667, 2504922, 356316

Abstract:

A probe apparatus configured to measure a set of electrical characteristics in a plasma processing chamber, the plasma processing chamber including a set of plasma chamber surfaces configured to be exposed to a plasma is disclosed. The probe apparatus includes a collection disk structure configured to be exposed to the plasma, whereby the collection disk structure is coplanar with at least one of the set of plasma chamber surfaces. The probe apparatus also includes a conductive path configured to transmit the set of electrical characteristics from the collection disk structure to a set of transducers, wherein the set of electrical characteristics is generated by an ion flux of the plasma. The probe apparatus further includes an insulation barrier configured to substantially electrically separate the collection disk and the conductive path from the set of plasma chamber surfaces.

US Patent:

7347915, Mar 25, 2008

Filed:

Jan 5, 2006

Appl. No.:

11/326934

Inventors:

Douglas L. Keil - Fremont CA, US
Wan-Lin Chen - Sunnyvale CA, US
Eric A. Hudson - Berkeley CA, US
S. M. Reza Sadjadi - Saratoga CA, US
Mark H. Wilcoxson - Piedmont CA, US

Assignee:

LAM Research Corporation - Fremont CA

International Classification:

H01L 21/00

US Classification:

15634547, 15634543

Abstract:

A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

US Patent:

7413672, Aug 19, 2008

Filed:

Apr 4, 2006

Appl. No.:

11/398306

Inventors:

Douglas L. Keil - Fremont CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

G01L 21/30
G01R 31/00

US Classification:

216 59

Abstract:

Methods and apparatus for detecting and/or deriving the absolute values of and/or the relative changes in parameters such as the plasma potential and the ion flux using a Planar Ion Flux (PIF) probing arrangement are disclosed. The detected and/or derived values are then employed to control plasma processing processes.

US Patent:

7455748, Nov 25, 2008

Filed:

Jun 20, 2003

Appl. No.:

10/600191

Inventors:

Douglas L. Keil - Fremont CA, US
Lumin Li - Santa Clara CA, US
Eric A. Hudson - Berkeley CA, US
Reza Sadjadi - Saratoga CA, US
Eric H. Lenz - Pleasanton CA, US
Rajinder Dhindsa - San Jose CA, US
Ji Soo Kim - Pleasanton CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

C23F 1/00
H01L 21/306
C23C 16/00

US Classification:

15634546, 118723 E

Abstract:

A plasma processing apparatus for processing a substrate is provided. A plasma processing chamber with chamber walls is provided. A substrate support is provided within the chamber walls. At least one confinement ring is provided, where the confinement ring and the substrate support define a plasma volume. A magnetic source for generating a magnetic field for magnetically enhancing physical confinement provided by the at least one confinement ring is provided.