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Douglas L Keil

age ~61

from West Linn, OR

Also known as:
  • Douglas Keil
  • Douglas Leonard Keil
  • Doulas Keil
  • Doug Keil
  • Keil Doulas

Douglas Keil Phones & Addresses

  • West Linn, OR
  • Clackamas, OR
  • Alameda, CA
  • 34421 Montgomery Pl, Fremont, CA 94555 • 510-8942510
  • Lake Forest, IL
  • Rohnert Park, CA
  • Madison, WI
  • 1062 Meek Way, West Linn, OR 97068

Work

  • Company:
    Lam research
    Jun 2012 to Sep 2013
  • Position:
    Senior staff physicist

Education

  • School / High School:
    University of Wisconsin-Madison

Awards

Authored or co-authored over 20 publications (7 refereed) in leading internationally recognized Journals. (e.g. Journal of Vacuum Science and Technology (JVST), Journal of the Electrochemical Society). Publication list and reprints available upon request. List includes a widely read invited JVST critical review article on dual damascene plasma etch processing. • Patents: US6,217,786 US6,268,260 US6540885 US6630407 US702611 US6780569, US7455748, US7319316 US7413672 US7479207 US7578301. An additional 11 other patent applications are in process. Most of these patents focused on plasma processes and/or sensors. Additional patent details available upon request.

Industries

Semiconductors

Resumes

  • Douglas Keil Photo 1

    Senior Staff Physicist At Lam Research

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  • Position:
    Senior Staff Physicist at Lam Research
  • Location:
    Tualatin, Oregon
  • Industry:
    Semiconductors
  • Work:
    Lam Research since Jun 2012
    Senior Staff Physicist

    Novellus Systems 2010 - Jun 2012
    Senior Technologist

    Lam Research 1997 - 2009
    Senior Staff Process Engineer / Engineering Manager

    Tegal Corporation 1995 - 1996
    Process Engineer

    University of Wisconsin, Department of Nuclear Engineering Jan 1989 - Aug 1995
    Research Assistant: - Phaedrus Tandem Mirror Group
  • Education:
    University of Wisconsin-Madison
    University of Wisconsin-Milwaukee
  • Honor & Awards:
    Authored or co-authored over 20 publications (7 refereed) in leading internationally recognized Journals. (e.g. Journal of Vacuum Science and Technology (JVST), Journal of the Electrochemical Society). Publication list and reprints available upon request. List includes a widely read invited JVST critical review article on dual damascene plasma etch processing. Patents: US6,217,786 US6,268,260 US6540885 US6630407 US702611 US6780569, US7455748, US7319316 US7413672 US7479207 US7578301. An additional 11 other patent applications are in process. Most of these patents focused on plasma processes and/or sensors. Additional patent details available upon request.

Amazon

Dear Dad

Dear Dad

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Realistic portrayal of an adolescent's journey through cancer treatment. This vivid story is told through the unfiltered voice of 14-year-old Dustin as letters to his dad. Emotional, inspiring and humorous, Dustin describes situational friendships, love/hate relationships with caregivers, strains on...


Author
Douglas Keil

Binding
Paperback

Pages
216

Publisher
CreateSpace Independent Publishing Platform

Publication Date
2016-03-14

ISBN #
1522976760

EAN Code
9781522976769

ISBN #
1

Barcats

BarCats

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During the spontaneous act of saving the BarCats from certain death, Ethan meets and falls in love with Annie, a mysterious woman who is sentenced to prison while trying to protect her Mafia uncle. Ethan finds himself in the crosshairs of the Feds and the mob as he risks all to obtain the release o...


Author
Douglas Keil

Binding
Paperback

Pages
432

Publisher
CreateSpace Independent Publishing Platform

Publication Date
2014-03-23

ISBN #
1495458164

EAN Code
9781495458163

ISBN #
2

Changing Toronto: Governing Urban Neoliberalism

Changing Toronto: Governing Urban Neoliberalism

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By exploring the formative years of the New City of Toronto (between 1995 and 2005, the period just before, during, and after metropolitan amalgamation), Changing Toronto analyzes the political, social, and environmental challenges of living in, and governing, a major metropolitan city region that b...


Author
Julie-Anne Boudreau, Roger Keil, Douglas Young

Binding
Paperback

Pages
256

Publisher
University of Toronto Press, Higher Education Division

Publication Date
2009-05-01

ISBN #
1442600934

EAN Code
9781442600935

ISBN #
3

Us Patents

  • Profile Control Of Oxide Trench Features For Dual Damascene Applications

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  • US Patent:
    6540885, Apr 1, 2003
  • Filed:
    Mar 28, 2001
  • Appl. No.:
    09/821427
  • Inventors:
    Douglas Keil - Fremont CA
    Eric Wagganer - Milpitas CA
    Bryan A. Helmer - Fremont CA
  • Assignee:
    Lam Research Corp. - Fremont CA
  • International Classification:
    C23C 1400
  • US Classification:
    20419233, 20419235, 216 38, 216 39, 216 59, 216 67
  • Abstract:
    Methods for etching a trench into a dielectric layer are provided. One exemplary method controls an ion-to-neutral flux ratio during etching so as to achieve a neutral limited regime in an ion assisted etch mechanism where the neutral limited regime causes bottom rounding. The method includes modulating physical sputtering causing microtrenching to offset the bottom rounding so as to produce a substantially flat bottom trench profile. Some notable advantages of the discussed methods of etching a trench into a dielectric layer includes the ability to eliminate the intermediate etch stop layer. Elimination of the etch stop layer will decrease fabrication cost and process time. Additionally, the elimination of the intermediate stop layer will improve device performance.
  • Apparatus And Method For Controlling Plasma Potential

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  • US Patent:
    2011002, Feb 3, 2011
  • Filed:
    Oct 14, 2010
  • Appl. No.:
    12/905046
  • Inventors:
    Douglas Keil - Fremont CA,
    Lumin Li - Santa Clara CA,
    Reza Sadjadi - Saratoga CA,
    Eric Hudson - Berkeley CA,
    Eric Lenz - Pleasanton CA,
    Rajinder Dhindsa - San Jose CA,
  • Assignee:
    Lam Research Corporation - Fremont CA
  • International Classification:
    H01L 21/306
  • US Classification:
    15634548
  • Abstract:
    An apparatus is provided for semiconductor wafer plasma processing. The apparatus includes a chamber having a lower electrode and an upper electrode disposed therein. The lower electrode is defined to transmit a radiofrequency current through the chamber to generate a plasma within the chamber. The lower electrode is also defined to support a semiconductor wafer in exposure to the plasma. The upper electrode is disposed above and in a spaced apart relationship with the lower electrode. The upper electrode is defined by a doped semiconductor material. A doping concentration within the upper electrode varies radially from a center to a periphery of the upper electrode. The electric potential of the upper electrode influences an electric potential of the plasma within the chamber.
  • Plasma Etching Of Dielectric Layer With Selectivity To Stop Layer

    view source
  • US Patent:
    2002014, Oct 3, 2002
  • Filed:
    Mar 30, 2001
  • Appl. No.:
    09/820692
  • Inventors:
    Ting Chien - Cupertino CA,
    Christine Nelson - Santa Clara CA,
    Douglas Keil - Fremont CA,
  • International Classification:
    H01L021/302
    H01L021/461
  • US Classification:
    438/710000
  • Abstract:
    A semiconductor manufacturing process wherein a dielectric layer is plasma etched with selectivity to an underlying and/or overlying stop layer such as a silicon nitride layer. The etchant gas includes a hydrogen-free fluorocarbon reactant such as CFgas wherein y/x 1.5, an oxygen-containing gas such as Oand a carrier gas such as Ar. The etch rate of the dielectric layer can be at least 10 times higher than that of the stop layer. Using a combination of CF, Oand Ar, it is possible to obtain dielectric: nitride etch selectivity of greater than 30:1 and nitride cornering etch selectivity of greater than 20:1. The process is useful for etching vias, contacts, and/or trenches of a self-aligned contact (SAC) or self-aligned trench.
  • Apparatus And Method For Controlling Plasma Potential

    view source
  • US Patent:
    2008000, Jan 10, 2008
  • Filed:
    Jul 10, 2006
  • Appl. No.:
    11/456545
  • Inventors:
    Douglas Keil - Fremont CA,
    Lumin Li - Santa Clara CA,
    Reza Sadjadi - Saratoga CA,
    Eric Hudson - Berkeley CA,
    Eric Lenz - Pleasanton CA,
    Rajinder Dhindsa - San Jose CA,
  • International Classification:
    C23F 1/00
    C23C 16/00
  • US Classification:
    118723 E, 15634547
  • Abstract:
    An apparatus is provided for semiconductor wafer plasma processing. The apparatus includes a chamber having a lower electrode and an upper electrode disposed therein. The lower electrode is defined to transmit a radiofrequency current through the chamber to generate a plasma within the chamber. The upper electrode is disposed above the lower electrode and is electrically isolated from the chamber. A voltage source is connected to the upper electrode. The voltage source is defined to control an electric potential of the upper electrode relative to the chamber. The electric potential of the upper electrode as controlled by the voltage source is capable of influencing an electric potential of the plasma to be generated between the lower and upper electrodes.
  • Methods For Automatically Characterizing A Plasma

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  • US Patent:
    2009032, Dec 31, 2009
  • Filed:
    Jun 2, 2009
  • Appl. No.:
    12/477007
  • Inventors:
    Douglas Keil - Fremont CA,
    Jean-Paul Booth - Boullay les Troux,
    Christopher Thorgrimsson - Fremont CA,
  • International Classification:
    G01N 27/62
  • US Classification:
    324464
  • Abstract:
    A method for automatically characterizing plasma during substrate processing is provided. The method includes collecting a set of process data, which includes at least data about current and voltage. The method also includes identifying a relevancy range for the set of process data, wherein the relevancy range includes a subset of the set of process data. The method further includes determining a set of seed values. The method yet also includes employing the relevancy range and the set of seed values to perform curve-fitting, wherein the curve-fitting enables the plasma to be automatically characterized.
  • Capacitively-Coupled Electrostatic (Cce) Probe Arrangement For Detecting Dechucking In A Plasma Processing Chamber And Methods Thereof

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  • US Patent:
    2010000, Jan 14, 2010
  • Filed:
    Jul 7, 2009
  • Appl. No.:
    12/498939
  • Inventors:
    Jean-Paul Booth - Boullay les Troux,
    Douglas L. Keil - Fremont CA,
  • International Classification:
    H01L 21/683
  • US Classification:
    361234
  • Abstract:
    A method for identifying a signal perturbation characteristic of a dechucking event within a processing chamber of a plasma processing system is provided. The method includes executing a dechucking step within the processing chamber to remove a substrate from a lower electrode, wherein the dechucking step includes generating plasma capable of providing a current to neutralize an electrostatic charge on the substrate. The method also includes employing a probe head to collect a set of characteristic parameter measurements during the dechucking step. The probe head is on a surface of the processing chamber, wherein the surface is within close proximity to a substrate surface. The method further includes comparing the set of characteristic parameter measurements against a pre-defined range. If the set of characteristic parameter measurements is within the pre-defined range, the electrostatic charge is removed from the substrate and the signal perturbation characteristic of the dechucking event is detected.
  • Apparatus To Detect Fault Conditions Of A Plasma Processing Reactor

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  • US Patent:
    2011002, Jan 27, 2011
  • Filed:
    Oct 5, 2010
  • Appl. No.:
    12/898342
  • Inventors:
    Douglas Keil - Fremont CA,
    Eric Hudson - Berkeley CA,
    Chris Kimball - Fremont CA,
    Andreas Fischer - Castro Valley CA,
  • Assignee:
    Lam Research Corporation - Fremont CA
  • International Classification:
    G06F 17/00
    G06F 15/00
  • US Classification:
    700110, 702183
  • Abstract:
    A method of fault detection for use in a plasma processing chamber is provided. The method comprises monitoring plasma parameters within a plasma chamber and analyzing the resulting information. Such analysis enables detection of failures and the diagnosis of failure modes in a plasma processing reactor during the course of wafer processing. The method comprises measuring the plasma parameters as a function of time and analyzing the resulting data. The data can be observed, characterized, compared with reference data, digitized, processed, or analyzed in any way to reveal a specific fault. Monitoring can be done with a detector such as a probe, which is preferably maintained within the plasma chamber substantively coplanar with a surface within the chamber, and directly measures net ion flux and other plasma parameters. The detector is preferably positioned at a grounded surface within the reactor such as a grounded showerhead electrode, and can be of a planar ion flux probe (PIF) type or a non-capacitive type. Chamber faults that can be detected include a build-up of process by-products in the process chamber, a helium leak, a match re-tuning event, a poor stabilization rate, and a loss of plasma confinement. If the detector is a probe, the probe can be embedded in a part of a plasma processing chamber and can comprises one or more gas feed-through holes.
  • Apparatus And Method For Controlling Plasma Potential

    view source
  • US Patent:
    2011002, Feb 3, 2011
  • Filed:
    Oct 14, 2010
  • Appl. No.:
    12/905041
  • Inventors:
    Douglas Keil - Fremont CA,
    Lumin Li - Santa Clara CA,
    Reza Sadjadi - Saratoga CA,
    Eric Hudson - Berkeley CA,
    Eric Lenz - Pleasanton CA,
    Rajinder Dhindsa - San Jose CA,
  • Assignee:
    Lam Research Corporation - Fremont CA
  • International Classification:
    H01L 21/306
  • US Classification:
    15634548
  • Abstract:
    A chamber includes a lower electrode and an upper electrode. The lower electrode is defined to transmit a radiofrequency current through the chamber and to support a semiconductor wafer in exposure to a plasma within the chamber. The upper electrode is disposed above and in a spaced apart relationship with the lower electrode. The upper electrode is electrically isolated from the chamber and is defined by a central section and one or more annular sections disposed concentrically outside the central section. Adjacent sections of the upper electrode are electrically separated from each other by a dielectric material. Multiple voltage sources are respectively connected to the upper electrode sections. Each voltage source is defined to control an electric potential of the upper electrode section to which it is connected, relative to the chamber. The electric potential of each upper electrode section influences an electric potential of the plasma within the chamber.

News

Doctors should reconsider some medications after fracture, researchers say

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  • Sarah Berry and Dr. Douglas Keil, researchers at Harvard who were not involved with the new study, wrote in a commentary published in JAMA Internal Medicine with the study. "A thoughtful review should include a discussion of reducing or eliminating medications associated with falls and bone loss wh
  • Date: Aug 22, 2016
  • Category: Health
  • Source: Google

Classmates

Douglas Keil Photo 2

Douglas Keil

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Schools:
New Underwood High School New Underwood SD 1957-1961
Community:
Linda Schell, Jean Bessette, Thomas Bruns, Dennis Anderson, Howard Knuppe, Milton Tschoepe, Thomas Weyer, Richard Aby, Noel Sorenson, Peggy Cox, Carol Dockter, Larry Shinost

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