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Fuhan Liu

age ~78

from Atlanta, GA

Also known as:
  • Liu Fuhan
1100 Holly St, Atlanta, GA 30318404-8757454

Fuhan Liu Phones & Addresses

  • 1100 Holly St, Atlanta, GA 30318 • 404-8757454
  • Stoughton, MA
  • Lawrenceville, GA

Us Patents

  • Chip-Last Embedded Interconnect Structures

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  • US Patent:
    8536695, Sep 17, 2013
  • Filed:
    Mar 8, 2012
  • Appl. No.:
    13/415503
  • Inventors:
    Fuhan Liu - Atlanta GA,
    Nitesh Kumbhat - Atlanta GA,
    Venkatesh Sundaram - Alpharetta GA,
    Rao R. Tummala - Greensboro GA,
  • Assignee:
    Georgia Tech Research Corporation - Atlanta GA
  • International Classification:
    H01L 23/12
    H01L 21/4763
    H05K 1/00
    H05K 1/03
  • US Classification:
    257700, 257758, 257774, 257E23041, 257E23145, 361748, 174255, 174262, 438637, 438667
  • Abstract:
    The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
  • Thin-Film Capacitor Structures Embedded In Semiconductor Packages And Methods Of Making

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  • US Patent:
    2010027, Oct 28, 2010
  • Filed:
    Apr 20, 2010
  • Appl. No.:
    12/763433
  • Inventors:
    DAVID ROSS MCGREGOR - Apex NC,
    Lynne E. Dellis - Willow Spring NC,
    Fuhan Liu - Atlanta GA,
    Deepukumar M. Nair - Cary NC,
    Venkatesh Sundaram - Alpharetta GA,
  • Assignee:
    GEORGIA TECH RESEARCH CORPORATION - Wilmington DE
  • International Classification:
    H01L 29/86
    H01L 21/768
    H01L 21/50
    H01L 23/522
  • US Classification:
    257532, 438654, 438106, 257774, 257E21585, 257E21499, 257E23145, 257E29325
  • Abstract:
    Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.
  • Thin-Film Capacitor Structures Embedded In Semiconductor Packages And Methods Of Making

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  • US Patent:
    2010027, Oct 28, 2010
  • Filed:
    Apr 20, 2010
  • Appl. No.:
    12/763444
  • Inventors:
    Lynne E. Dellis - Willow Spring NC,
    Fuhan Liu - Atlanta GA,
    David Ross McGregor - Apex NC,
    Venkatesh Sundaram - Alpharetta GA,
    Deepukumar M. Nair - Cary NC,
  • Assignee:
    GEORGIA TECH RESEARCH CORPORATION - Wilmington DE
  • International Classification:
    H01L 29/92
    H01L 21/50
  • US Classification:
    257532, 438125, 257E21499, 257E29342
  • Abstract:
    Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.
  • Through Package Via Structures In Panel-Based Silicon Substrates And Methods Of Making The Same

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  • US Patent:
    2012026, Oct 18, 2012
  • Filed:
    Apr 16, 2012
  • Appl. No.:
    13/448064
  • Inventors:
    VENKATESH V. SUNDARAM - Alpharetta GA,
    Fuhan Liu - Atlanta GA,
    Rao R. Tummala - Greensboro GA,
    Qiao Chen - Atlanta GA,
  • Assignee:
    Georgia Tech Research Corporation - Atlanta GA
  • International Classification:
    H01L 23/495
    H01L 21/768
  • US Classification:
    257666, 438667, 257E21597, 257E23041
  • Abstract:
    The various embodiments of the present invention provide a low cost, low electrical loss, and low stress panel-based silicon interposer with TPVs. The interposer of the present invention has a thickness of about 100 microns to 200 microns and such thickness is achieved without utilizing a carrier and further wherein no grinding, bonding, or debonding methods are utilized, therefore distinguishing the interposer of the present invention from prior art embodiments.
  • Through-Package-Via (Tpv) Structures On Inorganic Interposer And Methods For Fabricating Same

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  • US Patent:
    2013011, May 16, 2013
  • Filed:
    Mar 3, 2011
  • Appl. No.:
    13/582453
  • Inventors:
    Venkatesh Sundaram - Alpharetta GA,
    Fuhan Liu - Atlanta GA,
    Rao R. Tummala - Greensboro GA,
    Vijay Sukumaran - Atlanta GA,
    Vivek Sridharan - Atlanta GA,
    Qiao Chen - Atlanta GA,
  • Assignee:
    Georgia Tech Research Corporation - Atlanta GA
  • International Classification:
    H01L 23/48
    H01L 21/768
  • US Classification:
    257774, 438639
  • Abstract:
    The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs.

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