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Helia Naeimi

age ~42

from Sunnyvale, CA

Also known as:
  • Helia Farajidana
1057 Iris Ave, Sunnyvale, CA 94086

Helia Naeimi Phones & Addresses

  • 1057 Iris Ave, Sunnyvale, CA 94086
  • Santa Clara, CA
  • San Diego, CA
  • Pasadena, CA

Us Patents

  • Energy Harvesting Based On User-Interface Of Mobile Computing Device

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  • US Patent:
    8134341, Mar 13, 2012
  • Filed:
    May 4, 2009
  • Appl. No.:
    12/435378
  • Inventors:
    Helia Naeimi - Santa Clara CA,
    Qing Ma - Saratoga CA,
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H02J 7/00
  • US Classification:
    320137, 320128
  • Abstract:
    Embodiments of the invention relate to a mobile computing device with ambient energy harvesting capability. Embodiments of the invention, when manually operated by a user, convert the kinetic motion of a part of the user's hand, applied onto a controller of the device, to electrical energy. The energy can be used to power the device, or to charge the battery of the device. Embodiments of the invention include an electrical power storage device disposed in a housing, a display screen attached to the housing to display a plurality of user-interactive interfaces, and a manually operable input controller interactable with the interfaces and being coupled to an energy transformer in the housing to electrically charge the power storage device when operated.
  • Hybrid Error Correction Code (Ecc) For A Processor

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  • US Patent:
    8316283, Nov 20, 2012
  • Filed:
    Feb 26, 2010
  • Appl. No.:
    12/713623
  • Inventors:
    Helia Naeimi - Santa Clara CA,
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H03M 13/00
    G01R 31/28
    G06F 11/00
  • US Classification:
    714777, 714758, 714738
  • Abstract:
    In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.
  • Deterministic Addressing Of Nanoscale Devices Assembled At Sublithographic Pitches

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  • US Patent:
    20070127280, Jun 7, 2007
  • Filed:
    May 25, 2004
  • Appl. No.:
    10/853907
  • Inventors:
    Andre DeHon - Pasadena CA,
    Helia Naeimi - Pasadena CA,
  • International Classification:
    G11C 5/06
  • US Classification:
    365063000
  • Abstract:
    A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.
  • Platform Energy Harvesting

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  • US Patent:
    20110156406, Jun 30, 2011
  • Filed:
    Jan 25, 2010
  • Appl. No.:
    12/657656
  • Inventors:
    Qing Ma - Saratoga CA,
    Helia Naeimi - Santa Clara CA,
  • International Classification:
    F03G 7/08
  • US Classification:
    290 1 A
  • Abstract:
    Presented herein are approaches for using mother boards and/or other masses, already in a platform
  • Data With Appended Crc And Residue Value And Encoder/Decoder For Same

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  • US Patent:
    20120079348, Mar 29, 2012
  • Filed:
    Sep 24, 2010
  • Appl. No.:
    12/890513
  • Inventors:
    Helia Naeimi - Santa Clara CA,
  • International Classification:
    H03M 13/05
    G06F 11/10
  • US Classification:
    714763, 714E11034
  • Abstract:
    A semiconductor chip is described having ECC decoder circuitry disposed along any of: i) an interconnect path that resides between an instruction execution core and a cache; ii) an interconnect path that resides between an instruction execution core and a memory controller; and, iii) an interconnect path that resides between a cache and a memory controller. The ECC decoder circuitry has an input register to receive data, CRC values associated with the data and residue information associated with the data.
  • Error Management Across Hardware And Software Layers

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  • US Patent:
    20120221884, Aug 30, 2012
  • Filed:
    Feb 28, 2011
  • Appl. No.:
    13/036826
  • Inventors:
    Nicholas P. Carter - Hillsboro OR,
    Donald S. Gardner - Mountain View CA,
    Eric C. Hannah - Pebble Beach CA,
    Helia Naeimi - Santa Clara CA,
    Shekhar Y. Borkar - Beaverton OR,
    Matthew Haycock - Beaverton OR,
  • International Classification:
    G06F 11/07
  • US Classification:
    714 2, 714E11023
  • Abstract:
    Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error.
  • Number Representation And Memory System For Arithmetic

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  • US Patent:
    20140074902, Mar 13, 2014
  • Filed:
    Sep 7, 2012
  • Appl. No.:
    13/606998
  • Inventors:
    Helia NAEIMI - Santa Clara CA,
    Ralph NATHAN - Santa Clara CA,
    Shih-Lien L. LU - Portland OR,
    John L. GUSTAFSON - Santa Clara CA,
  • Assignee:
    INTEL CORPORATION - Santa Clara CA
  • International Classification:
    G06F 7/483
  • US Classification:
    708495
  • Abstract:
    A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value.

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