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Kevin J Uram

age ~62

from Hayward, CA

Also known as:
  • Kevin Uram
  • Kevin Juram
  • Keivin Uram

Kevin Uram Phones & Addresses

  • Hayward, CA
  • 2946 Sorrento Way, Union City, CA 94587 • 510-9720129
  • 11 Traci Ln, Hopewell Jct, NY 12533 • 845-2276159
  • Hopewell Junction, NY
  • Glenham, NY
  • Las Vegas, NV
  • Butler, PA
  • Carmel, NY
  • Fremont, CA

Us Patents

  • Advanced Damascene Planar Stack Capacitor Fabrication Method

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  • US Patent:
    57539480, May 19, 1998
  • Filed:
    Nov 19, 1996
  • Appl. No.:
    8/752137
  • Inventors:
    Son Van Nguyen - San Jose CA
    Matthias Ilg - Fishkill NY
    Kevin J. Uram - Union City CA
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 2972
  • US Classification:
    257307
  • Abstract:
    Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.
  • Advanced Damascene Planar Stack Capacitor Fabrication Method

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  • US Patent:
    60279680, Feb 22, 2000
  • Filed:
    Nov 20, 1997
  • Appl. No.:
    8/975193
  • Inventors:
    Son Van Nguyen - San Jose CA
    Matthias Ilg - Fishkill NY
    Kevin J. Uram - Union City CA
  • Assignee:
    International Business Machines Corporation - Armonk NY
    Siemens Aktiengesellschaft - Munich
    Lam Research Corporation - Fremont CA
  • International Classification:
    H01L 218242
  • US Classification:
    438254
  • Abstract:
    Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.
  • Method For Forming Semiconductor Structure Using Modulation Doped Silicate Glasses

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  • US Patent:
    57704694, Jun 23, 1998
  • Filed:
    Dec 29, 1995
  • Appl. No.:
    8/578165
  • Inventors:
    Kevin J. Uram - Union City CA
    John K. Shugrue - Fremont CA
    Nathan P. Sandler - Fremont CA
    Son Van Nguyen - Hopewell Junction NY
    Matthias Ilg - Fishkill NY
  • Assignee:
    Lam Research Corporation - Fremont CA
  • International Classification:
    H01L 21316
  • US Classification:
    437240
  • Abstract:
    A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate glass structure is formed by depositing at least two alternating layers of heavily-doped silicate glass and lightly-doped silicate glass over the first layer. Both the heavily-doped silicate glass and lightly-doped silicate glass layers may comprise glass doped with both a first dopant and a second dopant. The first dopant may represent, for example, phosphorous, and the second dopant may represent, for example, boron.

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