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Shine C Chung

age ~70

from San Jose, CA

Also known as:
  • Shine Chung
  • Shine Alice Chung
  • Shine Alic Chung
  • Chien Chung Shine
  • Chung Shine
1617 Corte De Medea, San Jose, CA 95124

Shine Chung Phones & Addresses

  • 1617 Corte De Medea, San Jose, CA 95124
  • Santa Clara, CA
  • Cupertino, CA
  • Palo Alto, CA
  • 5988 Porto Alegre Dr, San Jose, CA 95120

Work

  • Position:
    Professional/Technical

Business Records

Name / Title
Company / Classification
Phones & Addresses
Shine Chung
Owner
Chung, Shine
Engineering Services Business Services at Non-Commercial Site · Engineering Services, Nsk
5988 Porto Alegre Dr, San Jose, CA 95120

Us Patents

  • Software-Controlled Cache Memory Compartmentalization

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  • US Patent:
    6434671, Aug 13, 2002
  • Filed:
    Sep 30, 1997
  • Appl. No.:
    08/940865
  • Inventors:
    Shine Chung - San Jose CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 1200
  • US Classification:
    711129, 711128, 711133, 711136, 711 3
  • Abstract:
    A method and apparatus for controlling compartmentalization of a cache memory. A cache memory including a plurality of storage components receives one or more externally generated cache compartment signals. Based on the one or more cache compartment signals, cache compartment logic in the cache memory selects one of the plurality of storage compartments to store data after a cache miss.
  • Circuit And System Of A High Density Anti-Fuse

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  • US Patent:
    20120147653, Jun 14, 2012
  • Filed:
    Dec 8, 2011
  • Appl. No.:
    13/314444
  • Inventors:
    Shine C. Chung - San Jose CA,
  • International Classification:
    G11C 17/08
  • US Classification:
    365103
  • Abstract:
    A high density anti-fuse cell can be built at the cross points of two perpendicular interconnect lines, such as active region lines, active and polysilicon lines, active and metal lines, or polysilicon and metal lines. The cell size can be very small. At least one of the anti-fuse cells have a thin oxide fabricated before, after, or between a diode in at least one contact holes at the cross points of the interconnect lines. The thin oxide of the anti-fuse cells at the cross points can be selected for rupture by applying supply voltages in the two perpendicular lines. In some embodiments, a diode can be created after thin oxide is ruptured so that explicitly fabricating a diode or opening a contact hole at the cross-point may not be necessary.
  • Programmable Resistive Memory Unit With Multiple Cells To Improve Yield And Reliability

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  • US Patent:
    20120320657, Dec 20, 2012
  • Filed:
    Aug 20, 2012
  • Appl. No.:
    13/590049
  • Inventors:
    Shine C. Chung - San Jose CA,
  • International Classification:
    G11C 11/36
    H01L 45/00
    G11C 11/02
    G11C 17/06
    G11C 17/16
  • US Classification:
    365 96, 365148, 365100, 365163, 365158, 257 5, 438381, 257E45002
  • Abstract:
    A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure.
  • Programmable Resistive Memory Unit With Data And Reference Cells

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  • US Patent:
    20120320656, Dec 20, 2012
  • Filed:
    Aug 20, 2012
  • Appl. No.:
    13/590047
  • Inventors:
    Shine C. Chung - San Jose CA,
  • International Classification:
    G11C 11/36
    G11C 17/16
    G11C 11/02
    G11C 17/06
  • US Classification:
    365 96, 365148, 365100, 365163, 365158
  • Abstract:
    A method and system of a programmable resistive memory having a plurality of programmable resistive memory units is disclosed. At least one of the programmable resistive memory units has at least one data cell and at least one reference cell. The data cell can have one programmable resistive element coupled to at least one diode as a program selector and also coupled to a bitline (BL). The reference cell can have a reference resistive element coupled to at least one reference diode as reference program selector and also coupled to a reference bitline (BLR). In one embodiment, the reference resistive element can have substantially the same material, structure, or shape of the programmable resistive element. In one embodiment, the reference diode can have the same material, structure, or shape of the diode serving as the program selector diode.
  • Multiple-State One-Time Programmable (Otp) Memory To Function As Multi-Time Programmable (Mtp) Memory

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  • US Patent:
    20120314473, Dec 13, 2012
  • Filed:
    Aug 20, 2012
  • Appl. No.:
    13/590050
  • Inventors:
    Shine C. Chung - San Jose CA,
  • International Classification:
    G11C 17/00
    G11C 17/16
  • US Classification:
    365 96, 365100
  • Abstract:
    A circuit, method, and system for using multiple-state One-Time Programmable (OTP) memory to function as a multiple-bit programmable (MTP) memory are disclosed. The OTP memory can have N(N>2) distinct resistance states, that can be differentiated by at least Nāˆ’1 reference resistances, can be functionally equivalent programmed Nāˆ’1 times. The multiple-state OTP memory can have a plural of multiple-state OTP cells that can be selectively programmed to a resistance state. The reference resistance can be set to determine a state of the from the programmed multiple-state OTP cells.
  • Multiple-Bit Programmable Resistive Memory Using Diode As Program Selector

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  • US Patent:
    20120314472, Dec 13, 2012
  • Filed:
    Aug 20, 2012
  • Appl. No.:
    13/590044
  • Inventors:
    Shine C. Chung - San Jose CA,
  • International Classification:
    G11C 11/21
    G11C 11/02
    G11C 17/16
    G11C 17/06
  • US Classification:
    365 96, 365148, 365100, 365163, 365158
  • Abstract:
    A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2(n>1) distinct resistance levels to store n-bit data, at least 2āˆ’1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.
  • Raising Programming Currents Of Magnetic Tunnel Junctions Using Word Line Overdrive And High-K Metal Gate

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  • US Patent:
    20120281464, Nov 8, 2012
  • Filed:
    Jul 16, 2012
  • Appl. No.:
    13/550262
  • Inventors:
    Shine Chung - San Jose CA,
    Tao-Wen Chung - Zhubei City,
    Chun-Jung Lin - Hsin-Chu,
    Yu-Jen Wang - Hsin-Chu,
    Hung-Sen Wang - Tainan,
  • Assignee:
    TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. - Hsin-Chu
  • International Classification:
    G11C 11/16
  • US Classification:
    365158
  • Abstract:
    A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.
  • Bipolar Junction Transistors And Methods Of Fabrication Thereof

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  • US Patent:
    20120264269, Oct 18, 2012
  • Filed:
    Jun 27, 2012
  • Appl. No.:
    13/535090
  • Inventors:
    Po-Yao Ke - Dashe Township,
    Tao-Wen Chung - Zhubei City,
    Shine Chung - San Jose CA,
    Fu-Lung Hsueh - Cranbury NJ,
  • Assignee:
    TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. - Hsin-Chu
  • International Classification:
    H01L 21/8222
  • US Classification:
    438309, 257E21608
  • Abstract:
    A method of forming a semiconductor device is provided. The method includes forming a first fin above a substrate, forming a first emitter region in a first portion of the first fin, forming a first collector region in a second portion of the first fin, and forming a first base region in a third portion of the first fin. The third portion of the first fin is disposed underneath a first gate electrode. The method further includes forming a second fin adjacent to the first fin and above the substrate. The second fin is composed of a semiconductor material. The method also includes forming a first base contact over the second fin. The first base contact is coupled to the first base region through the second fin, the substrate, and the first fin.

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