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Shine C Chung

age ~71

from San Jose, CA

Also known as:
  • Shine Chung
  • Shine Alice Chung
  • Shine Alic Chung
  • Chien Chung Shine
  • Chung Shine
Phone and address:
1617 Corte De Medea, San Jose, CA 95124

Shine Chung Phones & Addresses

  • 1617 Corte De Medea, San Jose, CA 95124
  • Santa Clara, CA
  • Cupertino, CA
  • Palo Alto, CA
  • 5988 Porto Alegre Dr, San Jose, CA 95120

Work

  • Position:
    Professional/Technical

Business Records

Name / Title
Company / Classification
Phones & Addresses
Shine Chung
Owner
Chung, Shine
Engineering Services Business Services at Non-Commercial Site · Engineering Services, Nsk
5988 Porto Alegre Dr, San Jose, CA 95120
Shine Chung
President
SMART MEMORY SUPERCOMPUTING, INC
5988 Porto Alegre Dr, San Jose, CA 95120

Us Patents

  • Software-Controlled Cache Memory Compartmentalization

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  • US Patent:
    6434671, Aug 13, 2002
  • Filed:
    Sep 30, 1997
  • Appl. No.:
    08/940865
  • Inventors:
    Shine Chung - San Jose CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 1200
  • US Classification:
    711129, 711128, 711133, 711136, 711 3
  • Abstract:
    A method and apparatus for controlling compartmentalization of a cache memory. A cache memory including a plurality of storage components receives one or more externally generated cache compartment signals. Based on the one or more cache compartment signals, cache compartment logic in the cache memory selects one of the plurality of storage compartments to store data after a cache miss.
  • Method And Apparatus For Using Smart Memories In Computing

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  • US Patent:
    6807614, Oct 19, 2004
  • Filed:
    Mar 14, 2002
  • Appl. No.:
    10/099440
  • Inventors:
    Shine C. Chung - San Jose CA 95120
  • International Classification:
    G06F 1200
  • US Classification:
    711168, 709107, 709108
  • Abstract:
    A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.
  • Algorithm Mapping, Specialized Instructions And Architecture Features For Smart Memory Computing

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  • US Patent:
    6970988, Nov 29, 2005
  • Filed:
    Jul 19, 2002
  • Appl. No.:
    10/199745
  • Inventors:
    Shine C. Chung - San Jose CA, US
  • International Classification:
    G06F013/00
  • US Classification:
    711168, 711104
  • Abstract:
    A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.
  • High Voltage Cmos Switch With Reduced High Voltage Junction Stresses

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  • US Patent:
    7135914, Nov 14, 2006
  • Filed:
    Mar 24, 2004
  • Appl. No.:
    10/808122
  • Inventors:
    Yue-Der Chih - Hsin-Chu, TW
    Shine Chung - San Jose CA, US
  • Assignee:
    Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu
  • International Classification:
    G05F 3/02
  • US Classification:
    327543, 327328
  • Abstract:
    A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.
  • Decoupling Capacitor Design

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  • US Patent:
    7301217, Nov 27, 2007
  • Filed:
    Nov 19, 2004
  • Appl. No.:
    10/993711
  • Inventors:
    Shine Chien Chung - San Jose CA, US
  • Assignee:
    Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu
  • International Classification:
    H01L 29/00
    H01L 29/94
  • US Classification:
    257532, 257E29345, 3613062, 361734
  • Abstract:
    A thin-dielectric unit capacitor is disclosed having a first node coupled to a first circuit connection point and a second node coupled to a second circuit connection point. It further contains a first and second thin-dielectric capacitors connected in series between the first and second nodes, wherein a thickness of a gate dielectric for each thin-dielectric capacitor is less than 50 angstroms.
  • Electrical Fuses With Redundancy

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  • US Patent:
    7405989, Jul 29, 2008
  • Filed:
    Mar 7, 2005
  • Appl. No.:
    11/074920
  • Inventors:
    Shine Chien Chung - San Jose CA, US
  • Assignee:
    Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu, Taiwan
  • International Classification:
    G11C 17/18
  • US Classification:
    3652257, 365200, 36523006, 36523008
  • Abstract:
    The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the same. The fuse cell includes a first set of electrical fuses having at least one electrical fuse contained therein, and a second set of electrical fuses having at least one electrical fuse for providing redundancy to at least one fuse of the first set, wherein if one of the first set of electrical fuses is defective, at least one of the second set of the electrical fuses can be programmed to provide a redundancy function of the defective fuse.
  • Algorithm Mapping, Specialized Instructions And Architecture Features For Smart Memory Computing

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  • US Patent:
    7546438, Jun 9, 2009
  • Filed:
    Jul 5, 2005
  • Appl. No.:
    11/175559
  • Inventors:
    Shine C. Chung - San Jose CA, US
  • International Classification:
    G06F 9/45
  • US Classification:
    711202, 711201, 715247, 715263, 715771, 717109, 717149
  • Abstract:
    A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.
  • Voltage-Control Oscillator Circuits With Combined Mos And Bipolar Device

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  • US Patent:
    7663445, Feb 16, 2010
  • Filed:
    Sep 24, 2008
  • Appl. No.:
    12/237187
  • Inventors:
    Shine Chung - San Jose CA, US
    Fu-Lung Hsueh - HisnChu, TW
  • Assignee:
    Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu
  • International Classification:
    H03B 5/12
  • US Classification:
    331117R, 331117 FE, 331177 R, 331108 C
  • Abstract:
    A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.

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