Taku Uchino

US Patent:

7076405, Jul 11, 2006

Filed:

Sep 14, 2000

Appl. No.:

09/661919

Inventors:

Taku Uchino - Los Angeles CA, US

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki

International Classification:

G06G 17/10

US Classification:

703 2, 703 13, 703 14, 716 1, 716 2, 716 4

Abstract:

The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of stages. (1) At the outset, output signal waveforms and occurrence probabilities thereof at the first stage of the logic gates are calculated by the use of signal waveforms and occurrence probabilities thereof at primary input terminals of the integrated circuit; (2) next, output signal waveforms and occurrence probabilities thereof at the second stage of the logic gates are calculated by the use of the output signal waveform and the occurrence probability thereof at the primary input terminals and the output signal waveform and the occurrence probability thereof at the first stage of the logic gates; and (3) then, output signal waveforms and occurrence probabilities thereof at the n-th stage (n is a natural number) of the logic gates are calculated by the use of the output signal waveform and the occurrence probability thereof at the primary input terminals and the output signal waveform and the occurrence probability thereof at the (n-1)th stage of the logic gates. Thereby, types of the respective elementary waveforms, occurrence probabilities and signal correlations are calculated relating to signals located on each wiring of each stage inside of the integrated circuit and occurring within a predetermined time period.