Vladimir Rodov

Location:

Seattle, WA

Industry:

Semiconductors

Work:

US Patent:

6399996, Jun 4, 2002

Filed:

Jul 20, 2000

Appl. No.:

09/620074

Inventors:

Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 77095

US Classification:

257484, 257471, 257622

Abstract:

A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, and a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body.

US Patent:

6404033, Jun 11, 2002

Filed:

Jul 20, 2000

Appl. No.:

09/620653

Inventors:

Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 27095

US Classification:

257484, 257471, 257622

Abstract:

A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current.

US Patent:

6420225, Jul 16, 2002

Filed:

Mar 13, 2001

Appl. No.:

09/805815

Inventors:

Paul Chang - Saratoga CA
Vladimir Rodov - Redondo Beach CA
Geeng-Chuan Chern - Cupertino CA
Charles Lin - Fremont CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 218234

US Classification:

438237, 438167, 438173, 438586

Abstract:

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

US Patent:

6426541, Jul 30, 2002

Filed:

Dec 1, 2000

Appl. No.:

09/729127

Inventors:

Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 27095

US Classification:

257472, 257475

Abstract:

A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with sidewalls of the grooved surface and ohmic contacts with top portions of the grooved surface. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current. The ohmic contacts of the metal layer increase forward current and reduce forward voltage of the Schottky diode.

US Patent:

6448160, Sep 10, 2002

Filed:

Apr 6, 2000

Appl. No.:

09/544730

Inventors:

Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 2144

US Classification:

438527, 438109, 438134, 438209, 438350, 438658

Abstract:

A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor. The channel regions are defined by using the photoresist mask for the gate oxide with the photoresist mask isotropically etched to expose a peripheral portion of the gate oxide (and gate electrode) with ions thereafter implanted through the exposed gate for forming the channel region. The source/drain (e. g.

US Patent:

6498367, Dec 24, 2002

Filed:

Mar 8, 2000

Appl. No.:

09/520546

Inventors:

Paul Chang - Saratoga CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 2976

US Classification:

257341, 257330, 257339

Abstract:

A power rectifier having low on resistance, fast recovery time and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i. e. , with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common conductive layer. This provides a low V path through the channel regions of the MOSFET cells to the contact metallization on the other side of the integrated circuit. A thin gate structure is formed annularly around pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and V.

US Patent:

6515330, Feb 4, 2003

Filed:

Jan 2, 2002

Appl. No.:

10/037495

Inventors:

Gary M. Hurtz - Pleasanton CA
Vladimir Rodov - Redondo Beach CA
Geeng-Chuan Chern - Cupertino CA
Paul Chang - Saratoga CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 2976

US Classification:

257328, 257341

Abstract:

A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.

US Patent:

6537860, Mar 25, 2003

Filed:

Dec 18, 2000

Appl. No.:

09/739732

Inventors:

Hidenori Akiyama - Miyagi, JP
Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Haru Ohkawa - Miyagi, JP
Yasuo Ohtsuki - Miyagi, JP
Vladimir Rodov - Redondo Beach CA

Assignee:

APD Semiconductor, Inc. - San Jose CA
Fujifilm Microdevices Company, Ltd. - Miyagi

International Classification:

H01L 21332

US Classification:

438135, 438217, 438223, 438289, 438291, 438306, 438527

Abstract:

A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.